1. Field of the Invention
The present invention relates to a polycide gate electrode in a semiconductor device, and more particularly to a gate electrode structure for a MOS (Metal Oxide Semiconductor) type transistor having a dial gate structure for use in N-type and P-type polycide gate electrodes, and a manufacturing method thereof.
2. Description of the Prior Art
Description will be given as to a conventional method for manufacturing a semiconductor device having a dual gate structure in which N-type and P-type polycide gates are used for a gate electrode. Here, a polycide gate electrode for an N-type MOS transistor will be explained with reference to FIG. 7. Further, a TEG (Test Element Group) for a transistor device is exemplified for the brief explanation.
A P-type well 12 is formed on a silicon substrate 10 as a semiconductor substrate, and a field oxide film 14a for separating an device is formed. A gate oxide film 14b having a thickness of 10 nm is formed on a transistor forming portion. A polysilicon film is then formed on the entire surface so as to have a thickness of 10 nm by the LP-CVD (Low Pressure—Chemical Vapor Deposition) method. The polysilicon film in a P-type MOS transistor forming region is masked with a resist in a photolithography process, and implantation of the N-type impurity ion (phosphorus, arsenic and others) is carried out. The impurity diffusion is performed by the heat treatment after removing the resist so that a polysilicon film 16 (which will be simply referred to as an impurity diffused polysilicon film hereinafter) in which the N-type impurity is diffused is formed. Subsequently, a titanium silicide film (TiSi2) 18 having a thickness of 5 nm is formed on the polysilicon film having the impurity diffused polysilicon film as an impurity diffusion preventing film. A tungsten silicide film (WSix) 20 is thereafter formed on the titanium silicide film as a refractory metal silicide film so as to have a thickness of 100 nm. Further, a nitride film 22 having a thickness of 100 nm is formed on the tungsten film for insulation. This state is shown in FIG. 7(a).
Thereafter, a gate electrode pattern is formed by the photolithography and etching processes. The P-type MOS transistor forming region is masked with the resist in the photolithography process, and impurity ion implantation is carried out in order to form an N-diffusion layer 24 having an LDD (lightly Doped Drain) structure. This state is shown in FIG. 7(b).
After removing the resist, the oxidation process is effected with respect to the silicon substrate including the gate electrode pattern so that the oxide film 50 is formed on the side surface of the gate electrode. Then, in accordance with the LP-CVD method, the nitride film having a thickness of 300 to 400 nm is formed on the gate electrode which is exposed together with the oxide film on the gate electrode side surface. The nitride film is subjected to the anisotropic etching to form a second spacer 28 on the side surface of the gate electrode. Further, the gate electrode and the exposed gate oxide film in the P-type MOS transistor forming region are masked with the resist by the photolithography process, and the impurity ion plantation for forming the N+diffusion layer 30 for the source and the drain is carried out. This state is shown in FIG. 7(c).
An insulating film 52 such as the oxide film having a thickness of 400 to 800 nm is formed on the gate electrode, the exposed gate electrode oxide film and the field oxide film for insulation by the CVD method, and the surface of this insulating film 52 is smoothed. Thereafter, an opening portion 33 for a contact is formed by the photolithography and etching processes. This state is shown in FIG. 7(d). A metal 55 such as tungsten is embedded in the contact opening portion 33. A metal film such as aluminum is formed on the insulating film 52 including the metal 55 so as to have a thickness of 500 to 800 nm. A wiring 54 is formed by the photolithography and etching processes. This state is shown in FIG. 7(e).
FIG. 8(a) is a schematic plan view showing a TEG pattern after forming the contact opening portion. FIG. 8(b) is a view showing the cross-sectional shape taken along the 8(b)—8(b) line in FIG. 8A. The cross-sectional shape shown in FIG. 7(d) corresponds to the line 7(d)—7(d) in FIG. 8(a). Since the dual gate structure is provided, the N-type well 13 is formed on the side of the PMOS transistor as shown in FIGS. 8(a) and 8(b) which are schematic plan view and a cross sectional view, respectively. Further, the following process is carried out with respect to the gate electrode polysilicon on the PMOS transistor side as similar to the method for forming the impurity diffusion polysilicon on the N-type MOS transistor side. The polysilicon in the N-type MOS transistor forming region is masked with the resist in the photolithography process and the P-type impurity ion (which is mainly boron) is imoplanted in the polysilicon film on the PMOS transistor side. The P-type impurity is diffused by the heat treatment after removing the resist so that the P-type impurity diffused polysilicon film 17 is formed. Therefore, as shown in the cross-sectional view of FIG. 8(b), the N-type impurity diffused region and the P-type impuriyt diffused region exist in the polysilicon film formed in one step.
In the above-mentioned method for manufacturing the gate electrode for the MOS transistor, however, there are the following problems. The N-type diffused region and the P-type diffused region exist in the polysilicon film formed in one step. The impurity diffusion preventing film is formed for preventing the mutual diffusion of the N-type impurity and the P-type impurity. In the oxidizing process for forming the oxide film in the diffusion layer forming region for the source and the drain, since the impurity diffusion preventing film is provided in the lower layer of tungsten, the silicon is not supplied from the impurity doped polysilicon. There occurs abnormal oxidization such as that a refractory metal oxide film (W2O3) which is an oxide of tungsten is formed. This abnormal oxide portion results in a pattern failure.